The invention pertains to analog-to-digital converters.
Analog-to-digital converters (ADCs) have existed for decades and are a key factor in the quality and speed of many test systems. One type of commonly used ADC is the flash ADC. A flash ADC is advantageous in many applications in that 1) it is easy to construct, 2) it has good matching, and 3) it has little intrinsic delay (i.e., it can perform fast A/D conversions).
An exemplary flash ADC is illustrated in FIG. 9. The ADC comprises a resistor network, a plurality of comparators, and an encoder. The resistor network serves to provide a different reference voltage to each of the comparators. Thus, when an analog voltage signal, VIN, is received by each of the comparators, each comparator compares the analog voltage signal to a different reference voltage. If the analog voltage signal is greater than a comparator""s reference voltage, the comparator drives its output high. If the analog signal is less than a comparator""s reference voltage, the comparator drives its output low. In this manner, the comparators generate a thermometer code output (i.e., an output in which bits are consecutively asserted, beginning with a least significant bit). The thermometer code output generated by the comparators is then converted to a binary digital signal (B3, B2, B1) via the encoder.
Although the flash ADC is often relied on for its simplicity and speed, its advantages must sometimes be weighed against a number of disadvantages. One of its disadvantages is a high component count. Although the 3-bit ADC shown in FIG. 9 only requires eight resistors, eight comparators, and an encoder, an 8-bit ADC would require 256 resistors, 256 comparators, and an encoder. A flash ADC""s resistor and comparator count therefore grows exponentially with respect to the number of bits in its output (i.e., an N-bit flash ADC requires 2N resistors and 2N comparators).
Another disadvantage of the flash ADC is its high aspect ratio. To maintain good matching, each of a flash ADC""s 2N resistor and comparator slices is typically stacked end-to-end. Since the number of stages in a flash ADC (i.e., resistor, comparator, and encoder) remains constant regardless of the value of N, a flash ADC with even a modest value of N will have a high aspect ratio. A high aspect ratio is problematic in that it makes a flash ADC difficult to integrate with other components on a die.
Related to the problem of high aspect ratio is the problem of input impedance mismatch. Input impedance mismatch results from the variance in signal route lengths needed to supply the analog voltage signal, VIN, to each of a flash ADC""s comparators. One can appreciate that this problem is exacerbated by higher values of N.
Other disadvantages of the flash ADC include a high input capacitance and excessive power dissipation. As the value of N is increased, the parasitic capacitance seen by the analog voltage signal, VIN, grows exponentially. Likewise, the power consumed by a flash ADC grows exponentially.
In a first embodiment of the invention, an analog-to-digital converter comprises first and second comparator stages, a voltage reference stage, a switching stage, and an encoder. The first comparator stage receives an analog signal and a threshold and outputs a control signal. The voltage reference stage receives the control signal and outputs one of two or more sets of reference voltages. The second comparator stage receives the analog signal, as well as the set of reference voltages output from the voltage reference stage, and outputs a thermometer code in response to comparisons of the analog signal to the reference voltages. The switching stage receives the control signal, and in response thereto, variously couples inputs of the encoder to: bits of the thermometer code output from the second comparator stage, a first potential, or a second potential.
In a second embodiment of the invention, a method for converting analog signals to digital signals commences with the comparison of an analog signal, VIN, to (VMAXxe2x88x92VMIN)/2, where VMAX and VMIN define an expected voltage range for VIN. In response to VIN being greater than (VMAXxe2x88x92VMIN)/2, the LSB inputs of an encoder are driven to a first potential, and the MSB inputs of the encoder are determined by comparing VIN to a number of reference voltages ranging from (VMAXxe2x88x92VMIN)/2 to VMAX. In response to VINbeing less than (VMAXxe2x88x92VMIN)/2, the MSB inputs of the encoder are driven to a second potential, and the LSB inputs of the encoder are determined by comparing VIN to a number of reference voltages ranging from VMIN to (VMAXxe2x88x92VMIN)/2. A digital signal is then output from the encoder.
In a third embodiment of the invention, a method for converting analog signals to digital signals commences as an analog signal is input to a comparator stage. At or about the same time, the analog signal is compared to at least one threshold. In response thereto, a voltage reference stage is programmed to deliver one of two or more sets of reference voltages to the comparator stage. Also, and in response to the comparison(s) of the analog signal to the threshold(s), different sets of an encoder""s inputs are coupled to either: a first potential, a second potential, or outputs of the comparator stage. A digital signal is then output from the encoder.